1. Field of the Invention
The present invention relates in general to a semiconductor substrate and a method for producing the same and, more particularly to, a non-porous semiconductor layer formed on a porous semiconductor layer and a method for forming the same. Further, the present invention relates to a method of evaluating the shape and state of a surface of a semiconductor substrate, in particular, a porous layer thereof.
The present invention relates also to a semiconductor substrate utilized as a base member for integrated circuits using mainly MOSFETs and bipolar-transistors and a method for forming the same.
2. Related Background Art
Research has been conducted in the integrated-circuit (IC) technologies for silicon-based semiconductor devices to work out a silicon-on-insulator (SOI) structure, in which a monocrystalline silicon film is disposed on an insulator, because the structure reduces parasitic capacitance and facilitates element isolation, thus improving the operation speed of transistor, decreasing the power consumption, improving the integration density, and reducing the total cost.
To form the SOI structure there has been available the Fully Isolation by Porous Silicon (FIPOS) method proposed by Imai in the 1970s through the early 1980s (K. Imai, Solid State Electronics 24 (1981), p. 159). The FIPOS method utilizes the accelerated oxidation phenomenon of porous silicon to form an SOI structure but has a problem that it can inherently form a surface silicon layer only in the shape of islands.
One of the SOI formation technologies attracting the world attention in recent years is the wafer bonding technology, surrounding which have been proposed various methods because the SOI structure provides arbitrariness in the thickness of a surface silicon layer and a buried silicon oxide layer as well as good crystallinity of the surface silicon layer.
Although the bonding method, by which wafers are bonded without an adhesive agent or any other intermediate layers, was proposed originally by Nakamura et al., its research has advanced since 1984, when J. B. Lasky et al. reported the method of thinning one of two bonded wafers and the operation of a MOS transistor formed thereon (J. B. Lasky, S. R. Stiffler, F. R. White, and J. R. Abernathey, Technical Digest of the International Electron Devices Meeting (IEEE, New York, 1985), p. 684).
By the method by Lasky et al., a first wafer which is a monocrystalline silicon wafer incorporated with boron at a high concentration and having formed thereon a low-concentration or n-type epitaxial silicon layer and a second wafer having an oxide film formed on a surface thereof are provided and rinsed, as necessary, and are then brought into close contact with each other, so that the two wafers are bonded to each other by the van der Waals force. The two wafers undergo heat treatment to form covalent bonds therebetween, whereby the bonding strength is enhanced to such a level as not to disturb the production of devices. Then, the first wafer is etched on its back side with a mixture liquid of hydrofluoric acid, nitric acid, and acetic acid, to selectively remove the p+ silicon wafer so that only the epitaxial silicon layer remains on the second wafer, which is called also the single etch-stop method. However, the ratio of the etch rate for the p+ silicon to that for the epitaxial silicon (pxe2x88x92 or n type) is as low as several 10s, thus requiring further improvements to leave a uniform thickness of an epitaxial silicon layer on the entire wafer surface.
Thus, a method has been worked out for conducting selective etching twice. That is, as a first substrate is provided a low-impurity-concentration silicon wafer substrate on a surface of which are stacked a p++ type Si layer and a low-impurity-concentration layer; then this first wafer is bonded to such a second wafer as described above. Then, the first substrate is thinned by grinding, polishing, or any other mechanical method on its back side. Next, the first substrate undergoes selective etching until the whole surface of the p++ Si layer buried in the first substrate is exposed. In this case, selective etching due to the difference in the impurity concentration of the substrate is effected by using an alkaline liquid such as ethylene diamine pyrocatechol, KOH, etc. Then, the exposed p++ Si layer is selectively removed by the selective etching by use of a mixture liquid of hydrofluoric acid, nitric acid, and acetic acid as is the case with the above-mentioned Lasky method, so that only the above-mentioned low-impurity-concentration monocrystalline Si layer is transferred onto the second substrate, which is called the double etch-stop method. This method, by carrying out selective etching a plurality of times, has proved to improve the overall etch selectivity, resulting in a better uniformity in the thickness of the surface Si layer in the SOI.
However, it may be anticipated that the thinning of layers by means of selective etching utilizing the above-mentioned difference in the impurity concentration or composition of the substrate would be affected by the depth profile of the impurity concentration. That is, if the wafers, after the bonding, are heat-treated at a high temperature in order to enhance the bonding strength, the impurity in the buried layer diffuses, so that the etch selectively degrades, resulting in lowering in the uniformity of film thickness. Therefore, the heat treatment after bonding had to be carried out at 800xc2x0 C. or less. Moreover, because each of the plural times etching would provide a low etch selectivity, the controllability at the time of mass-production was of concern.
In contrast to the above-mentioned method, in which etch selectivity depends on a difference in impurity concentration or composition, Japanese Patent Application Laid-Open No. 5-21338 employs a difference in structure to provide etch selectivity. That is, this method implements an etch selectivity as high as 100,000 due to structural difference between porous silicon with a surface area per unit volume such as 200 m2/cm3 and non-porous silicon, which is called a selective etching method utilizing a structural difference using porous silicon. By this method, a surface of a monocrystalline Si wafer given for a first substrate is anodized to make porous, after which a non-porous monocrystalline silicon layer is epitaxially grown thereon to provide the first substrate. Then, it is bonded to a second substrate and undergoes heat treatment as necessary to enhance the bonding strength. Subsequently grinding, polishing or the like is carried out to remove the back side of the first substrate, thus exposing the porous silicon layer in its entirety. Next, the porous silicon is selectively removed by etching to, with the result that the above-mentioned non-porous monocrystalline silicon layer is transferred onto the second substrate. Since a high etch selectivity as much as 100,000 was obtained, the uniformity in the thickness of the SOI layers obtained was impaired little by the etching, reflecting the uniformity of the monocrystalline silicon layer during the epitaxial growth as such. That is, as is the case with a commercially available CVD epitaxial growth apparatus, this method attains an in-wafer uniformity, for example 1.5% to 3% or less, for the SOI-Si layer. This method uses, as the material for selective etching, the porous silicon which is used as the material for selective oxidation in the FIPOS method. Therefore, this method does not limit the porosity to about 56% but prefers a rather low value of about 20%. Note here that the method for producing SOI structures disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-21338 was named ELTRAN (trademark) in a report by Yonehara et al. (T. Yonehara, K. Sakaguchi, N. Sato, Appl. Phys. Lett. 64 (1994), p. 2108).
Also, since porous silicon will not become the structural member of a final product, the structural change and the coarsening of porous silicon are tolerated as far as they will not impair the etch selectivity.
Sato et al., the inventor of the present invention, conducted a Chemical Vapor Deposition (CVD) method using a SiH2Cl2 gas as the source gas for the epitaxial growth on a porous substance at process temperatures of 1040xc2x0 C. for heat treatment before epitaxial growth and 900 to 950xc2x0 C. during epitaxial growth (N. Sato, K. Sakaguchi, K. Yamagata, Y. Fujiyama, and T. Yonehara, Proc. of the Seventh Int. Symp. on Silicon Mater. Sci. and Tech., Semiconductor Silicon, (Pennington, The Electrochem. Soc. Inc., 1994), p. 443).
To avoid structural coarsening of porous silicon during heat treatment at a high temperature, Sato et al. introduced, prior to the epitaxial growth step, a preoxidation step of forming a protective film at the walls of porous silicon pores to almost suppress the structural coarsening of the porous silicon layer involved in the heat treatment. The preoxidation is carried out, for example, at 400xc2x0 C. in oxygen atmosphere.
A key factor to this method is how to reduce the defects formed during the epitaxial growth of non-porous monocrystalline silicon on porous silicon. Thus made SOI wafers have stacking fault as the main defect and, reportedly, has a stacking fault density of 103 to 104/cm2 in an epitaxial silicon layer on porous silicon.
It is generally pointed out that stacking faults may degrade the dielectric strength of oxide films. This is considered because when a metal impurity precipitates at a dislocation portion surrounding a stacking fault, a leakage current of a p-n junction would increase, thereby degrading the life time of minority carriers. The other reports on the epitaxial growth on a porous substance did not refer to a crystal defect density of less than 103/cm2 by means of observation with an optical microscope after defect revealing etching with a lower detection limit. Although the probability of stacking faults of 103 to 104/cm2 being in a gate region of 1 xcexcm2 is as low as 0.0001 to 0.00001, as compared to a bulk silicon wafer, the defect density is still high and so expected to be revealed as decreases in the yield of IC production. For practical application of SOI wafers obtained by the above-mentioned method, it is necessary to reduce the stacking fault density to at least 1000/cm2.
Further, when non-porous monocrystalline silicon is epitaxially grown on a porous silicon layer, introduction of many stacking faults are caused by xe2x80x9cporous structurexe2x80x9d of a supporting base member for the epitaxial growth.
As the conventional method of evaluating or observing the porous structure, in particular, a surface shape and a surface state thereof, a method of directly observing them with SEM or the like is used but is complicated as means therefor. Therefore, a method of simply and easily evaluating them has been required.
A first object of the present invention is to provide a semiconductor substrate having a non-porous monocrystalline layer with decreased crystal defects on a porous silicon layer and a method for producing the substrate.
A second object of the present invention is to provide a substrate having a non-porous monocrystalline layer with less crystal defect density on an insulator and a method for producing the substrate.
A third object of the present invention is to provide a method of simply and easily evaluating the surface state of a porous layer and to decrease the stacking fault density of a thin film formed on a porous layer by utilizing the evaluation method.
According to a first aspect of the present invention, there is provided a method of producing a semiconductor substrate comprising a non-porous monocrystalline layer on a porous silicon layer, which comprises, before a step of forming the non-porous monocrystalline layer on the porous silicon layer, a step of heat-treating the porous silicon layer in an atmosphere not containing a source gas of the non-porous monocrystalline layer, wherein a condition of the heat treatment is determined such that a rate of change r for Haze values of the porous silicon layer surface before and after the heat treatment defined by (the Haze value of the porous silicon layer surface after the heat treatment)/(the Haze value of the porous silicon layer surface before the heat treatment) is in a predetermined range.
According to a second aspect of the present invention, there is provided the above-mentioned method, wherein the predetermined range is 1xe2x89xa6rxe2x89xa63.5.
According to a third aspect of the present invention, there is provided a method of producing a semiconductor substrate, which comprises a step of providing a substrate comprising a porous silicon layer, a heat treatment step of heat-treating the porous silicon layer, and a growth step of growing a non-porous monocrystalline layer on the porous silicon layer, wherein the heat treatment step is conducted in an atmosphere not containing a source gas of the non-porous monocrystalline layer such that the thickness of a portion which has been etched to be removed (hereinafter referred to as xe2x80x9cetched thicknessxe2x80x9d) of silicon due to the heat treatment is not more than 2 nm and that the rate of change r for the Haze value of the porous silicon layer surface defined by (the Haze value after the heat treatment)/(the Haze value before the heat treatment) satisfies the relationship of 1xe2x89xa6rxe2x89xa63.5.
According to a fourth aspect of the present invention, there is provided a method of producing a semiconductor substrate, which comprises a step of providing a first substrate comprising a porous silicon layer, a heat treatment step of heat-treating the porous silicon layer, a growth step of growing a non-porous monocrystalline layer on the porous silicon layer, and a step of transferring the non-porous monocrystalline layer grown on the first substrate onto a second substrate, wherein the heat treatment step is conducted in an atmosphere not containing a source gas of the non-porous monocrystalline layer such that the etched thickness of silicon due to the heat treatment is not more than 2 nm and that the rate of change r for the Haze value of the porous silicon layer surface defined by (the Haze value after the heat treatment)/(the Haze value before the heat treatment) satisfies the relationship of 1xe2x89xa6rxe2x89xa63.5.